| REN Yifan (任一凡),ZHANG Chunming,SONG Yidi.[J].高技术通讯(英文),2025,31(4):407~414 |
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| Design of a parallel configurable forward feedback equalization dual-mode high-speed SerDes transmitter |
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| DOI：10. 3772 / j. issn. 1006-6748. 2025. 04. 010 |
| 中文关键词: |
| 英文关键词: digital signal processing, digital-to-analog conversion, parallel configurable forward feedback equalization, dual-mode transmitter, source series termination driver, 4 ∶ 1 multiplexers |
| 基金项目: |
| Author Name | Affiliation | | REN Yifan (任一凡) | (School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121,P. R. China) | | ZHANG Chunming | | | SONG Yidi | |
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| 中文摘要: |
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| 英文摘要: |
| Four-level pulse amplitude modulation (PAM4) signals, recognized for enhanced energy efficiency and spectral utilization compared with non-return-to-zero ( NRZ) counterparts, have been adopted in multiple high-speed serializer/ deserializer (SerDes) standards, but NRZ modulation remains predominant in industrial applications. This paper introduces a UMC 28 nm CMOS-based parallel configurable forward feedback equalization ( FFE) dual-mode high-speed SerDes transmitter supporting 7-bit resolution with data rates of 56 Gb · s-1 NRZ and 112 Gb · s-1 PAM4, utilizing a hybrid architecture that integrates digital signal processing (DSP) with digital-to-analog conversion (DAC). The design processes parallel input signals and eight stored 8-bit tap coefficients through a configurable FFE multiplier module and parallel carry adder module, while achieving low-power serialization via low-speed 16 ∶ 4 multiplexers (MUXs) with two different 2 ∶ 1 MUXs and high-speed 4 ∶ 1 MUXs. A source series termination (SST) output network structure enhances lower power dissipation and higher output swing. Simulation results show that, under a 1. 05 V supply voltage and a channel loss of 19. 21 dB at 28 GHz, the output 56 Gb · s-1 NRZ eye diagram has an eye height of 70. 11 mV and an eye width of 12. 16 ps (0. 68 UI). The output 112 Gb · s-1 PAM4 eye diagram has an eye height of 20. 07 mV and an eye width of 7. 49 ps (0. 42 UI). The layout area of the dual-mode transmitter is 0. 079 mm2, and the total circuit power consumption is 74. 48 mW(energy efficiency is 1. 33 / 0. 67 pJ · bit-1). |
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