| XIE Xiaoyan(谢晓燕)*,JI Shentao*,ZHU Yun**,YANG Kun**,XIA Xinyuan**,WANG Shuxin*.[J].高技术通讯(英文),2022,28(1):40~47 |
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| Reconfigurable design of deblocking filter for variable block sizes |
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| DOI：10.3772/j.issn.1006-6748.2022.01.005 |
| 中文关键词: |
| 英文关键词: deblocking filter (DBF), high efficiency video coding (HEVC), array processor, dynamically reconfigurable |
| 基金项目: |
| Author Name | Affiliation | | XIE Xiaoyan(谢晓燕)* | (*School of Computing Science & Technology, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China)
(**School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China) | | JI Shentao* | (*School of Computing Science & Technology, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China)
(**School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China) | | ZHU Yun** | (*School of Computing Science & Technology, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China)
(**School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China) | | YANG Kun** | (*School of Computing Science & Technology, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China)
(**School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China) | | XIA Xinyuan** | (*School of Computing Science & Technology, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China)
(**School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China) | | WANG Shuxin* | (*School of Computing Science & Technology, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China)
(**School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, P.R.China) |
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| 中文摘要: |
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| 英文摘要: |
| Based on the flexible quadtree partition structure of coding tree units (CTUs), the deblocking filter (DBF) in high efficiency video coding (HEVC) consumes a lot of resources when implemented by hardware. It is difficult to achieve flexible switching between different sizes of coding blocks. Aiming at this problem, a reconfigurable implementation of DBF is proposed. Based on the dynamic programmable reconfigurable video array processor (DPRAP) with context switch reconfiguration mechanism, the runtime flexible switching of two coding block sizes is realized. The experimental results show that the highest work-frequency reaches 151.4MHz. Compared with the dedicated hardware architecture scheme, the resource consumption can be reduced by 28.1% while realizing the dynamic switching between algorithms of two coding block sizes. Compared with the results of HM16.0, by using a complete I-frame for testing, the average peak signal-to-noise ratio (PSNR) of the reconfigurable implementation proposed in this paper has increased by 3.0508dB, the coding quality has improved to a certain extent. |
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