| Zhang Mingke (张明科),Hu Qingsheng.[J].高技术通讯(英文),2015,21(2):205~211 |
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| A 10Gb/s combined equalizer in 0.18μm CMOS technology for backplane communication |
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| DOI：10.3772/j.issn.1006-6748.2015.02.013 |
| 中文关键词: |
| 英文关键词: analog equalizer, decision feedback equalizer (DFE), inductive peaking, current mode logic (CML) |
| 基金项目: |
| Author Name | Affiliation | | Zhang Mingke (张明科) | | | Hu Qingsheng | |
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| 中文摘要: |
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| 英文摘要: |
| This paper presents a 10Gb/s high-speed equalizer as the front-end of a receiver for backplane communication. The equalizer combines an analog equalizer and a two-tap decision-feedback equalizer in a half-rate structure to reduce the inter-symbol-interference (ISI) of the communication channel. By employing inductive peaking technique for the high-frequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decision-feedback equalizer optimizes the size of the CML-based circuit such as D flip-flops (DFF) and multiplex (MUX), shortening the feedback path delay and speeding up the operation considerably. Designed in the 0.18μm CMOS technology, the equalizer delivers 10Gb/s data over 18-in FR4 trace with 28-dB loss while drawing 27-mW from a 1.8-V supply. The overall chip area including pads is 0.6×0.7mm2. |
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