| Chen Yingmei (陈莹梅),Xu Zhigang,Wang Tao,Zhang Li.[J].高技术通讯(英文),2014,20(1):92~96 |
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| Design of 15 Gb/s inductorless limiting amplifier with RSSI and LOS indication in 65nm CMOS |
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| DOI：10.3772/j.issn.1006-6748.2014.01.015 |
| 中文关键词: |
| 英文关键词: limiting amplifier, receiver signal strength indictor (RSSI), loss of signal (LOS), full-wave rectifier, third order active feedback |
| 基金项目: |
| Author Name | Affiliation | | Chen Yingmei (陈莹梅) | | | Xu Zhigang | | | Wang Tao | | | Zhang Li | |
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| 中文摘要: |
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| 英文摘要: |
| A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed optical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. The receiver signal strength indictor (RSSI) can detect input signal power with 33dB dynamic range, and the limiting amplifier features a programmable loss of signal (LOS) indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER=10-12 and the layout area is only 0.53×0.72 mm2 because of no passive inductor. The total gain is over 41dB, and bandwidth exceeds 12GHz with 56mW power dissipation. |
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