| Wang Yangang(汪彦刚),Peng Silong.[J].高技术通讯(英文),2013,19(2):137~144 |
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| A reconfigurable low-cost memory-efficient VLSI architecture for video scaling |
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| DOI： |
| 中文关键词: |
| 英文关键词: video scaling, very-large-scale integration (VLSI) architecture, polyphase filter, reconfiguration |
| 基金项目: |
| Author Name | Affiliation | | Wang Yangang(汪彦刚) | | | Peng Silong | |
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| 中文摘要: |
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| 英文摘要: |
| A runtime reconfigurable very-large-scale integration (VLSI) architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scaling is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling applications and also verified by many widely acknowledged image quality measures. The reconfigurable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array (FPGA) devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework. |
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