文章摘要
王文波,毛陆虹,肖新东,谢生,张世林.一种7-8双模预分频Δ∑ Fractional-N频率综合器[J].高技术通讯(中文),2012,22(12):
一种7-8双模预分频Δ∑ Fractional-N频率综合器
A 7-8 dual pre divider Δ∑ fractional N frequency synthesizer
  修订日期:2012-02-06
DOI:
中文关键词: 超高频射频识别(UHF RFID)阅读器, 频率综合器, 压控振荡器(VCO), 7-8双模预分频, Δ∑调制器
英文关键词: ultra high frequency radio frequency identification (UHF RFID) reader, frequency synthesizer, voltage controlled oscillator (VCO), 7-8 dual pre divider, Δ∑ modulator
基金项目:863计划(2008AA04A102)资助项目
作者单位
王文波 天津大学电子信息工程学院 天津 
毛陆虹 天津大学电子信息工程学院 天津 
肖新东 天津大学电子信息工程学院 天津;中国兵器工业系统总体部 北京 
谢生 天津大学电子信息工程学院 天津 
张世林 天津大学电子信息工程学院 天津 
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中文摘要:
      设计了一种应用于超高频射频识别(UHF RFID)阅读器的Δ∑ Fractional N频率综合器。该频率综合器采用开关电容阵列结构实现了调谐范围为750~950MHz的压控振荡器,使用电流模式逻辑(CML)结构D触发器实现了7-8双模预分频,频率精度设计为1.98kHz,电路基于UMC 0.18μm 2层多晶6层金属CMOS工艺实现,芯片面积为1700μm×1950μm。仿真结果表明系统建立时间小于100μs。系统相位噪声的Matlab仿真结果为-115dBc/Hz@500kHz。测试结果显示电源电压1
英文摘要:
      A Δ∑ fraction N frequency synthesizer for single chip UHF RFID (ultra high frequency radio frequency identification) readers was designed and implemented. The design of the frequency synthesizer adopts a switch capacitor array to achieve its multiple band voltage controlled oscillator and tuning range of 750~950MHz, and uses a current module logic (CML) D flip flop to realize a dual 7-8 pre divider. The frequency accuracy of the frequency synthesizer was designed for 1.98kHz. The simulation result showed the setup time of the system was less than 100μs, and the Matlab simulation showed the system phase noise was -115dBc/Hz@500kHz. This synthesizer was fabricated in the UMC 0.18μm double poly six metal CMOS process technology, with a die size of 1700μm×1950μm. The experimental results showed that the chip dissipated a current of 15mA current under a supply voltage of 1.8V, the total phase noise was -111.45dBc/Hz@500kHz, and the output frequency was coincident with the preset.
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