| 卓蕊潋* **,石晶林* **,周一青* **,刘垚圻* **,陈洋***,赵诗琪*.基于卫星通信多模切换的射频资源池FPGA虚拟化技术研究[J].高技术通讯(中文),2026,36(2):137~146 |
| 基于卫星通信多模切换的射频资源池FPGA虚拟化技术研究 |
| Research on FPGA virtualization of RF resource pool for multi-mode bearer technology in satellite communications |
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| DOI：10. 3772 / j. issn. 1002 - 0470. 2026. 02. 003 |
| 中文关键词: 卫星通信； 射频资源池； 多模切换； 现场可编程门阵列虚拟化 |
| 英文关键词: satellite communication, radio frequency resource pool, multi-mode switching, field-programmable gate array virtualization |
| 基金项目: |
| 作者 | 单位 | | 卓蕊潋* ** | (*中国科学院计算技术研究所北京市移动计算与泛在设备重点实验室北京 100190)
(**中国科学院大学北京 100049)
(***北京中科晶上科技股份有限公司北京 100190) | | 石晶林* ** | | | 周一青* ** | | | 刘垚圻* ** | | | 陈洋*** | | | 赵诗琪* | |
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| 中文摘要: |
| 随着全球用户对通信需求的持续攀升，卫星网络正以前所未有的速度蓬勃发展，并呈现出多种异构体制相互融合、共同存在的趋势。然而，现有的卫星地面关口站架构受限于有限的硬件资源，其计算能力和存储能力均受到制约，进而导致系统灵活性和可扩展性不足，难以满足多模通信体制同时搭载以及快速切换的需求。为此，本文提出了一种基于射频资源池的虚拟化技术，该技术旨在在有限硬件资源的条件下，实现多用户多模制式算法的承载，并满足系统对多模制式切换时延的严格要求。论文提出了一种静态编译与动态编译相结合的编译方式，通过现场可编程门阵列（field-programmable gate array，FPGA）的局部动态配置，实现多种运算的快速切换，从而支持多种模式下波形的瞬时转换。仿真结果表明，采用动静结合的编译方式可节省50%的FPGA逻辑资源，且参数重配平均耗时40μs，仅为静态配置平均耗时420ms的万分之一，充分证明了该技术的可行性和实用性。 |
| 英文摘要: |
| With the continuous surge in global communication demands, satellite networks are experiencing unprecedented rapid development, characterized by the fusion and coexistence of multiple heterogeneous systems. This trend poses unprecedented challenges to the multi-mode switching capabilities of satellite ground gateways. To address this issue, this paper proposes a virtualization technology based on the radio frequency resource pool, which aims to enable the loading of multi-user and multi-mode algorithms under limited hardware resources while meeting the stringent requirements of the system for multi-mode switching delay. By adopting a compilation method that combines static and dynamic compilation, local dynamic configuration on the field-programmable gate array (FPGA) is achieved, facilitating rapid switching between multiple operations to support instant conversion of multi-mode waveforms. Simulation results demonstrate that the combined static-dynamic compilation method can save 50% of FPGA logic resources. Moreover, the average time for parameter reconfiguration is 40μs, which is merely one ten-thousandth of the average 420ms required for static configuration, thereby proving the feasibility and practicality of this technology. |
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