文章摘要
杨喜宁,周一青,陈洋.基于数据面加速器的工业5G协议处理架构研究[J].高技术通讯(中文),2023,33(10):1038~1046
基于数据面加速器的工业5G协议处理架构研究
High-performance protocol processing architecture with HW/SW collaboration for industrial 5G
  
DOI:10. 3772/ j. issn. 1002-0470. 2023. 10. 004
中文关键词: 工业5G; 软硬协同; 协议处理; 加速器
英文关键词: industrial 5G, SW/HW collaboration, protocol processing, accelerator
基金项目:
作者单位
杨喜宁 (中国科学院计算技术研究所处理器芯片全国重点实验室北京 100190) (中国科学院大学北京 100049) (移动计算与新型终端北京市重点实验室北京 100190) 
周一青  
陈洋  
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中文摘要:
      伴随5G标准的不断演进和商用网络的规模部署,5G已成为引领我国智能制造高质量发展的新引擎。与此同时,以高带宽、高频次小包通信为特征的工业应用也对5G终端基带芯片协议处理提出了挑战。本文提出一种以数据面加速器(DPA)为核心的高性能软硬件协同5G协议处理架构,该架构将异构芯片计算资源与协议处理功能进行了合理映射,并通过并行化设计大幅提升5G用户面数据处理性能。实验结果表明,相比纯软件的实现方案本文提出的协同架构在不同业务负载条件下,数据包处理时延平均下降28.3%,包处理通量平均提升38%。在0.5ms的时隙周期配置下,本文架构的数据包处理速率大于2000包/s,可以满足工业5G大规模现场节点集中式数据采集的需求。
英文摘要:
      With the continuous evolution of 5G standards and the large-scale deployment of commercial networks, 5G has become a new engine leading the high-quality development of intelligent manufacturing in China. At the same time, industrial applications characterized by high bandwidth and high frequency packet communication also pose challenges to 5G terminal baseband chip protocol processing. In this paper, a high-performance protocol processing architecture with collaboration of software and hardware based on data plane accelerator (DPA) is proposed. The architecture divides the software and hardware functions of 5G protocol processing reasonably, and improves the performance of 5G user plane data processing greatly through parallel design. Experimental results show that compared with the pure software implementation scheme, the cooperative architecture proposed in this paper can reduce the packet processing delay by 28.3% and increase the packet processing flux by 38% on average under different traffic loads. Considering the time slot configuration with 0.5ms, the packet processing rate of the proposed architecture is greater than 2000 packets/s, which can meet the centralized data collection of a mass of factory nodes for industrial 5G.
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