| 杨丽琼,章隆兵,肖俊华,王剑.高性能CPU电源Droop检测优化设计实现[J].高技术通讯(中文),2022,32(9):894~902 |
| 高性能CPU电源Droop检测优化设计实现 |
| Implementation of fast speed high accuracy Droop detection for high-performance CPU |
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| DOI：10.3772/j.issn.1002-0470.2022.09.002 |
| 中文关键词: 高性能中央处理器(CPU)； 供电检测； Droop Sensor |
| 英文关键词: high-performance central processing unit (CPU), voltage supply detection, Droop Sensor |
| 基金项目: |
| 作者 | 单位 | | 杨丽琼 | （计算机体系结构国家重点实验室（中国科学院计算技术研究所）北京 100190）
（中国科学院计算技术研究所北京 100190）
（中国科学院大学北京 100049） | | 章隆兵 | （计算机体系结构国家重点实验室（中国科学院计算技术研究所）北京 100190）
（中国科学院计算技术研究所北京 100190）
（中国科学院大学北京 100049） | | 肖俊华 | （计算机体系结构国家重点实验室（中国科学院计算技术研究所）北京 100190）
（中国科学院计算技术研究所北京 100190）
（中国科学院大学北京 100049） | | 王剑 | （计算机体系结构国家重点实验室（中国科学院计算技术研究所）北京 100190）
（中国科学院计算技术研究所北京 100190）
（中国科学院大学北京 100049） |
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| 中文摘要: |
| 高性能中央处理器(CPU)进入到纳米工艺设计时代，集成度和性能大幅度提高的同时，功耗和时钟之间的平衡优化已经成为当前面临的主要问题。物理供电寄生阻抗增加明显，功耗急速增加过程导致电源网络动态压降明显，抑制了主频进一步提高。本文提出了一种基于全数字快速高精度Droop Sensor的供电监测优化方法。该方法采用易于集成于处理器核数字域内的单数字供电Droop Sensor进行本地供电实时监测。当Droop Sensor检测到电压快速垂降时，实时指导所在处理器核的时钟域进行时钟降频，帮助处理器度过低压危险时期，待垂降结束后再恢复正常的时钟频率。实现了局部压降的针对性时钟优化，避免了整体功耗性能损失。本文采用12nm 数字工艺实现了Droop Sensor设计。仿真结果表明，该传感器可在100ps内进行一阶Droop的快速响应，帮助CPU度过瞬间大幅度的压降期；高阶Droop响应的阈值调节精度可达3%，支持CPU的供电水平多阈值控制。 |
| 英文摘要: |
| High-performance central processing unit (CPU) has already entered into the nano-process design era. The integration and performance of CPU are greatly improved, while power consumption and clock balance optimization has become a main issue. The increase of physical power supply parasitic impedance is obvious, and the process of rapid increase in power consumption leads to the dynamic voltage droop of power network, which inhibits the further improvement of the main frequency. In this paper, a power supply monitoring optimization method based on all digital fast and high-precision Droop Sensor is proposed. This method uses single digital power supply, easy to be integrated into the processor core digital domain for local power supply real-time monitoring. When Droop Sensor detects a rapid droop in voltage, the clock domain of the processor core is guided in real time for frequency’s modulation, helping the processor through periods of low-pressure hazard and returning to normal clock frequencies until the droop is over. The targeted clock optimization of local voltage droop is realized, which avoids the loss of overall power performance. The Droop Sensor design is realized using the 12nm digital process. The simulation results show that the sensor can respond quickly to the first-order Droop within 100ps, which can help the CPU through the instantaneous large pressure droop period, and the threshold adjustment accuracy of the high-order Droop response can reach 3%, which supports the power supply level multi-threshold control of the CPU. |
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